1. Field of the Invention
The present invention relates to a data pass control device for masking a write ringing in a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) and a method thereof and more particularly, to a data pass control device for masking a write ringing that occurs at the completion of the writing operation of the DDR SDRAM and a method thereof.
2. Description of the Related Art
A DDR SDRAM is generally a memory device that generates an internal synchronization clock clk generated from an external synchronization clock ext_clk through a DLL circuit or other circuit and then inputs/outputs data synchronously with the rising and falling edges of the internal synchronization clock clk. The internal synchronization clock clk is also referred as to a master clock master clk.
What is going to be described here in connection with the DDR SDRAM is one particular operation, that is, how to eliminate failure or malfunction of a memory device, caused by ringing during a write operation.
Typically, the ringing during the write operation is referred as to a write ring back phenomenon. When this write ring back occurs, an unwanted dummy write operation is performed due to the ringing of a data strobe signal at the last phase of the write operation and then existing data stored in a data latch is changed, resulting in a write error. The data strobe signal and data latch will be described later in detail.
Hereinafter, it will be appropriate to give definitions of signals used in this specification and then problems found in related art techniques will be described next.
<Definitions of Signals>
1. ext_clk: An external synchronization clock that is applied from the outside of the DDR SDRAM.
2. clk: An internal synchronization clock generated by receiving the external synchronization clock. This is an internal master clock, synchronizing data input/output. In other words, this is the master clock for controlling overall operations of the DDR SDRAM.
3. din: Data inputted from the outside during a write operation of the DDR SDRAM. This is the abbreviation of input data. Usually, a voltage level of the input data din is SSTL level. This input data din is applied to a data input buffer din_buffer.
4. ds: Data strobe signal inputted from the outside during a write operation of the DDR SDRAM. The ds signal, which will be described later, transfers the input data din onto global input/output lines gio. In general, voltage level of the ds signal is SSTL level. The ds signal is applied to a data strobe buffer ds_buffer.
5. din_buffer: A data input buffer. This amplifies the SSTL level of the input data din inputted from the outside during a write operation of the DDR SDRAM up to CMOS level. If the voltage level of the input data din is higher than a designated reference voltage level, a high level is outputted to output line in and a low level is outputted to output line inz. On the contrary, if voltage level of the input data din is lower than the designated reference voltage level, the high level is outputted to the output line inz and the low level is outputted to the output line in. Here, the output line inz denotes input bar (i.e./din). According to en_dinz signal (enable data input bar signal), the data input buffer din_buffer is disabled during a read operation but enabled during a write operation.
6. ds_buffer: A data strobe buffer. This amplifies the SSTL level of the data strobe signal ds inputted from the outside during a write operation of the DDR SDRAM up to CMOS level. If voltage level of the inputted data strobe signal ds is higher than a designated reference voltage (that is, a high level), an output signal rdinclk is outputted as a high level signal and a output signal fdinclk is outputted as a low level signal. On the other hand, if the voltage level of the data strobe signal ds is lower than the designated reference voltage (that is, a lower level), the rdinclk is outputted as a low level signal and the fdinclk is outputted as a high level signal. Here, the rdinclk is the abbreviation of a rising data input clock, and the fdinclk is the abbreviation of a falling data input clock. According to the en_dinz signal (enable data input bar signal), the data strobe buffer ds_buffer is disabled during a read operation but enabled during a write operation.
7. din_lat: A data latch means. In a case that an input signal ds of the data strobe buffer ds_buffer is on a rising edge, data outputted from the data input buffer din_buffer is synchronized with an output signal rdinclk of the data strobe buffer and then stored in the data latch means. In addition, in a case that an input signal ds of the data strobe buffer ds_buffer is on a falling edge, data outputted from the data input buffer din_buffer is synchronized with an output signal fdinclk of the data strobe buffer and then stored in the data latch means. The data din stored in the data latch means din_lat is transferred to the global input/output lines gio, in response to a control signal dinstb (data input strobe).
8. dis_diz: Based on an assumption that a data strobe signal ds is on a falling edge, an output signal of a controller outputting a disable level output signal dis_diz (disable data strobe bar) after receiving the fdinclk signal which is an output signal of the data strobe buffer ds_buffer. The disable level output signal dis_dsz is feedbacked to the data strobe buffer ds_buffer and as a result, the fdinclk signal pass is blocked (or masked). Afterwards, the disable level output signal dis_dsz becomes an enable level signal by the internal synchronization clock clk and thus, enables the data strobe buffer to pass the next fdinclk signal.
9. en_dinz: A signal that enables the data input buffer. din_buffer and the data strobe buffer ds_buffer during a write operation and disables the data input buffer din_buffer and the data strobe buffer ds_buffer during a read operation.
10. en_din: A signal having a voltage level opposite to the voltage level of en_dinz.
11. dinstb: A signal for synchronizing a data stored in the data latch means din_lat with the internal synchronization clock clk and transmitting to the global input/output lines gio.
Hereinafter it will be explained of related art techniques.
FIG. 1 is a schematic block diagram illustrating a data pass controller used in a write operation of a related art DDR SDRAM.
As shown in FIG. 1, the related art data pass controller includes an input buffer 100, a data strobe buffer 110, a data latch 120, and a data strobe buffer controller 130. Here, the data input buffer 100 is denoted by din_buffer; the data strobe buffer 110 is denoted by ds_buffer; and the data latch 120 is denoted by din_lat.
Since functions of each individual elements and their signals are already described above, the overall operation of the data pass controller will now be briefly described below and then a write ringing at the last phase of the write operation will be detailed next. Further referring to FIG. 1, FIG. 2 illustrates a waveform diagram of signals in FIG. 1.
First, the overall operation of the data pass controller depicted in FIG. 1 is as follows:
1) During a write operation, the data input buffer 100 and the data strobe buffer 110 are enabled according to en_dinz signal.
2) Data din inputted from the external is transferred to output lines in, inz through the data input buffer 100.
3) Data strobe signal ds applied in pulse type outputs pulse type of signals rdinclk, fdinclk through the data strobe buffer 110.
4) When the data strobe signal ds is on a rising edge, the data on the output lines in, inz of the data input buffer 100 is synchronized with the rdinclk signal and is stored in the data latch 120. On the other hand, when the data strobe signal ds is on a falling edge, the data on the output lines in, inz of the data input buffer 100 is synchronized with the fdinclk signal and is stored in the data latch 120.
5) The stored data in the data latch 120 is transferred to global input/output lines gio, in response to a data input strobe signal dinstb.
6) The output signal fdinclk at the step 3) is also applied to the data strobe buffer controller 130. In case that the data strobe signal ds is on the falling edge, the data strobe buffer controller 130 is synchronized with the fdinclk signal among the output signals of the data strobe buffer ds_buffer and outputs a disable level output signal dis_dsz (disable data strobe bar). This disable level output signal dis_dsz is feedbacked to the data strobe buffer ds_buffer and as a result, the fdinclk signal pass is blocked (or masked). By the internal synchronization clock clk, the disable level output signal dis_dsz becomes an enable level signal and enables the data strobe buffer 110 to pass next fdinclk signal (reference to FIG. 2).
With reference to FIGS. 1 and 2, the following will now describe the write ringing that occurs during the write operation.
As illustrated in FIG. 2, when the en_dinz signal is enabled to a low level, the data input buffer 100 and the data strobe buffer 110 are enabled. Therefore, the input data din is transferred to the output lines in, inz of the data input buffer 100. Still referring to FIG. 2, the data strobe signal ds is applied as a pulse type of signal. Moreover, assuming that the ringing does not occur, a data strobe signal made of four pulse signals has four rising edges and four falling edges, so that a total of 8 data will be stored in the data latch 120. For example, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, and DQ8 data will be inputted in sequence through an input line of the data input buffer 100.
More details are as follows:
1) In response to the rising edge of a first data strobe signal ds, the first data DQ1 is stored in the data latch 120.
2) In response to the falling edge of the first data strobe signal ds, the second data DQ2 is stored in the data latch 120. Here, a high pulse signal fdinclk is outputted in response to the falling edge of the first data strobe signal ds. Then the controller 130 receives the signal fdinclk and outputs a low level enable signal dis_dsz. The low level enable signal dis_diz is feedbacked to the data strobe buffer 110, to block (or mask) the generation of the fdinclk signal. As described above, the second data DQ2 is stored in the data latch 120 in response to the fdinclk signal generated before it is masked by the low level enable signal dis_dsz. Hence, the first data DQ1 and the second data DQ2 stored in the data latch 120 are transferred to the global input/output lines gio by the data input strobe signal dinstb. Accordingly, the first write operation is completed. The next step is, as shown in FIG. 2, that the output signal dis_dsz of the controller transits to a high level by the internal clock clk and enables the data strobe buffer ds_buffer. As a result of this, the data strobe buffer ds_buffer starts operating normally.
3) The operations of a second, a third, and a fourth data strobe signal ds on the rising and falling edges are identical with the ones described in steps 1) and 2).
4) However, in the case of the related art, as illustrated in FIG. 2, after the falling edge of the fourth data strobe signal ds, for some reason the ringing occurs when the data strobe signal ds turns back to the termination voltage or standby voltage. What happens in such case is that the signals rdinclk and fdinclk are generated at the rising and falling edges of the data strobe signal generated due to the ringing and as a result, an invalid data is applied to the data latch 120.